An FPGA CAD framework focused on rapid prototyping of new CAD algorithms. The framework is implemented in Java. At this moment packing, placement and routing algorithms are implemented in the framework.

What can I do with this tool flow?

• Packing:
  • Partitioning based packing: A multi-threaded implementation of a packer. Packing happens in two phases. Firstly the partitioningsbased packing and secondly the seed-based packing phase. A second phase is necessary to allow the packer to check architectural constraints.
• Placement:
  • Simulated Annealing based Placement
  • Placement with an iterative analytical solver based placement
  • Placement with Liquid: A placer that uses steepest gradient descent moves to place a design
• Routing:
  • Connection-based routing: a fast timing-driven connection based router.

Usage

Currently, the HES team is writing a user manual for the framework. Some parts of this toolflow require external packages, you can find these in the file "requirements".

To calculate point to point delays, vpr is used (see option --vpr_command). When compiling vpr, the macro PRINT_ARRAYS has to be defined in "place/timing_place_lookup.c".

License

see license file

Contact us

The FPGA Placement Framework is released by Ghent University, ELIS department, Hardware and Embedded Systems (HES) group (http://hes.elis.ugent.be).

If you encounter bugs, want to use the FPGA CAD Framework but need support or want to tell us about your results, please contact us. We can be reached at dries.vercruyce[at]ugent.be

Referencing the FPGA Placement Framework

If you use the FPGA CAD Framework in your work, please reference the following papers in your publications:

Packing: How preserving circuit design hierarchy during FPGA packing leads to better performance
Dries Vercruyce, Elias Vansteenkiste and Dirk Stroobandt
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems}, 37(3), pp. 629-642.

Placement: Liquid: High quality scalable placement for large heterogeneous FPGAs
Dries Vercruyce, Elias Vansteenkiste and Dirk Stroobandt
Field Programmable Technology (ICFPT), 2017 17th International Conference on. IEEE, 2017

Routing: CRoute: A fast high-quality timing-driven connection-based FPGA router
Dries Vercruyce, Elias Vansteenkiste and Dirk Stroobandt
accepted for publication

Contributors

Active Contributors

• Dries Vercruyce - dries.vercruyce@ugent.be
• Yun Zhou - yun.zhou@ugent.be
• Elias Vansteenkiste - Elias.Vansteenkiste@gmail.com

Past Contributors

• Arno Messiaen - Arno.Messiaen@gmail.com
• Seppe Lenders - Seppe.Lenders@gmail.com

Development

The FPGA CAD Framework is a work in progress, input is welcome.